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Implementing an FPGA / PCB co-design process

Intelligent design of the FPGA interface is an imperative when using FPGA devices to meet leading-edge system interface requirements such as DDR3. An FPGA interface design without PCB process integration or PCB routing consideration can lead to increased PCB costs and extended design times. The key, as this article demonstrates, is to consider connectivity as the foundation for a FPGA/PCB co-design process and the critical elements that are required for an effective implementation. Connectivity in this context is bidirectional movement of FPGA interface information between the FPGA and PCB domains.

Implementing an effective process-connectivity foundation enables the FPGA to be quickly incorporated into the PCB design. An important derivative of a connectivity solution is the repeatable creation of an FPGA interface definition that is optimized for both the FPGA and PCB. The results of this connectivity foundation are lower development costs and improved PCB quality.

FPGA proliferation
FPGA devices are ubiquitous in new product designs with approximately 100,000 design starts each year. No one argues that there are many benefits offered by FPGA technology. The industry leaders, Xilinx and Altera, both had sales in excess of $1 billion in 2007, with Xilinx approaching $2B.

There is a constant stream of new product offerings from the industry leaders that include Xilinx Virtex-5 FXT (high performance processing and I/O) and Virtex-4QV (space applications), Altera's Stratix IV (high density with 13.3 million gates), and Actel's IGLOO (low power). The diversity of offerings should be a system designer's dream.

The FPGA design process is well-defined with a suite of FPGA vendor-provided tools to support it, which includes Xilinx's ISE, Altera's Quartus II, and Actel's Libero IDE. As each new generation of FPGA is delivered, so are the tools that see constant investment...

... Life is good!

But now, this new cool design that works great in the FPGA has to go onto a circuit board. Most companies have made a minimal investment in a co-design PCB process, with the end result being a compromise on productivity and quality of results. Fig 1 shows a two-dimensional representation of co-design complexity. The FPGA device complexity is shown on the vertical axis and the PCB process complexity on the horizontal axis. The growing number of pins, I/O standards, process cores, and pin assignment rules add to the FPGA complexity. These device capabilities translate into PCB complexity in terms of pin swapping, symbol creation, routing, signal integrity, etc. The co-design process implemented must address the complexities determined by the device being used and the process objectives.

Implementing an FPGA / PCB co-design process 1
1. FPGA / PCB co-design complexity.
(Click this image to view a larger, more detailed version)

The simplistic co-design solution is a unidirectional process starting at the FPGA vendor's tool, going to schematic, and then finally to PCB layout. There may be some preliminary I/O planning, but in most cases the PCB designer lives with what comes down the road. This process may be inadequate for many needs and may require the addition of a pin swapping capability. Ultimately, the quality of the PCB is at stake as well as the time required to design it. A poor I/O assignment can lead to longer routing times, longer traces, additional signal layers, more vias, and possibly signal integrity issues.

FPGA usage spans a vast spectrum, from simple glue logic to system-on-programmable-device implementations. This huge array of implementations begs for a flexible and extensible FPGA/PCB co-design process. The foundation for the co-design process is connectivity – the ability to move domain-specific information across domains and transform the data to be useful in the destination domain.

For instance, building a FPGA schematic symbol is a foreign concept to the FPGA designer. But the pin assignments made in the FPGA domain in the form of a .pin or .pad file are represented as a wired symbol or symbol set in the PCB domain. These are two very different representations of the same information. Each representation brings value to the native domain. The domain-crossing of information should be bi-directional and void of manual, error prone activities. Implementing effective domain connectivity is the foundation on which a process is built.

Close the loop
The most effective FPGA/PCB co-design process is a closed loop with quality-of-results feedback coming from the PCB layout. The FPGA interface is then tuned based on this feedback, producing a high-quality FPGA/PCB integration. The various steps in the co-design process are as follows:

  • FPGA vendor support
  • Custom or generic components
  • PCB symbol generation
  • PCB schematic generation
  • FPGA I/O optimization

Each of these steps is described below in the context of an actual design...

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